The present invention relates generally to the field of semiconductor memories and more particularly to a novel method and apparatus for compensating for the effect of coupling between bit lines in multi-port memories.
In high density semiconductor memories, coupling capacitance between adjacent bit lines in the memory can corrupt the data that is written to or read from the memory. Two methods of avoiding the effects of coupling capacitance include providing extra spacing between the bit lines and shielding one bit line from the next bit line with power and ground conductors during layout of the memory. However, these methods are costly in terms of silicon area for high density memories. Moreover, even with proper spacing, it is often difficult to completely eliminate capacitive coupling.
U.S. Pat. No. 5,140,556 to Cho et al. discloses a single-port dynamic random access memory (DRAM) circuit having dummy cells, which are connected to twisted bit lines. The memory is divided into four equal segments, and the bit lines of adjacent memory cells are twisted between the segments to compensate for capacitive coupling. However, this patent does not address avoidance of coupling capacitance between bit lines of two or more ports, which are part of the same memory cell, in a multi-port memory. In addition, while this implementation can be used with custom memory devices, it is difficult, if not impossible, to implement this method in a memory compiler for embedded memory devices in which the number of rows in the memory is variable.
A method of compensating for coupling capacitance between bit lines of different ports of the same memory cell has been used by LSI Logic Corporation in their embedded memory cores. With multi-port memories, capacitive coupling can occur between the bit lines of different ports during simultaneous access (writing or reading) of different cells of the same column of the memory. With an LSI dual-port memory core, the internal bit lines (BLA and BLAN) of one of the two ports were switched (i.e. crossed) at the middle of each column of the memory. By crossing the internal bit lines of one port at the middle of the memory, the effects of capacitive coupling along the upper half of the memory is cancelled out by the capacitive coupling along the lower half of the memory.
Since the bit lines of one port were switched in the middle of the memory for one port, the data inputs and data outputs of that port were inverted when writing to or reading from the upper half of the memory, which saw an inversion in the crossed bit lines at the middle of the memory. This ensured that the same data could be written to and read from the upper half of the memory through the port with switched bit lines and through the port without switched bit lines.
Unfortunately, the above method of compensating for coupling capacitance has some inherent difficulties. In memory compiler applications, where the number of rows in the memory is variable, it is very difficult for the compiler algorithm to locate the bit line crossing location exactly in the middle of each column. Also, the row address bits, which identify whether the upper or lower half of the memory is being accessed, had to be decoded to determine whether the data inputs or data outputs had to be inverted for the port having the switched bit lines. This decoding can be very tedious and can become very difficult to implement in a memory compiler environment where the number of physical rows can vary.
To optimize the address decoding logic, the memory compiler algorithm is written to find a tolerance capacitance below which coupling between adjacent bit lines has no significant effect. This tolerance capacitance is then correlated to a maximum number of physical rows along which there is no compensation. The total memory array is then divided into two parts such that the maximum difference between the two parts is less than or equal to the tolerance size. Keeping this criterion in mind, the algorithm chooses a switch point to optimize the address decoding.
Although this algorithm reduces complexity of the address decoding somewhat, it is difficult for the memory compiler algorithm to find a good and reliable tolerance capacitance since the tolerance capacitance can vary significantly with process variation, amount of circuit noise and power bumps. The chances of silicon failure using the above-technique can be very high in some applications.
Consequently, it would be advantageous if an improved system and method existed compensating for coupling capacitance between adjacent bit lines in large multi-port memories. Further, it would be advantageous if a faster system and method existed for read/write operations while providing coupling capacitance compensation. It would be also be advantageous if a system and method existed for coupling capacitance compensation which is less restrictive in circuit design and did not require selection of an address bit.
Accordingly, the present invention is directed to a system and method for compensating for coupling capacitance between adjacent bit lines in multi-port memories. The present invention includes utilizing a modified core cell on the bit lines after switching the bit lines for the internal port. The modified core cell may have inverted connections to access transistors which results in writing the desired data into the cell correctly and more quickly.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.